MSX Village forum

@Z80 : La page suivante pourrait t'être également utile : http://openmsx.sourceforge.net/vdp-vram-timing/vdp-timing.html



Lors de la Nijmegen 2013, certains ont en effet entrepris d'enregistrer les différents signaux du/des VDP(s).

Tu peux éventuellement joindre Wouter Vermaelen ( vermaelen [dot] wouter @robase gmail [dot] com) afin de récupérer les données enregistrées.



EDIT :

Les données recueillies semblent disponibles à cette adresse : http://sourceforge.net/mailarchive/message.php?msg_id=30375119

et le lien direct est : http://damad.be/joost/nijmegen2013_VDP_timing_measurements.zip

Horizontal line timing



The VDP renders a full frame line-by-line. For each line the VDP (possibly) has to read some bitmap and sprite data from VRAM. It's logical to assume (and the measurements confirm this) that the data fetches within one line occur at the same relative positions as the corresponding data fetches of another line. So if we can figure out the details for one line, we can extrapolate this to a whole frame. Similarly we can assume that different frames will have similar relative timings. So really all we need to know is the timing of one line.



TODO: odd and even frames in interlace mode probably do have timing differences. Still need to investigate this.



Let's thus first look at what we already know about an horizontal display line. The 'V9938 Technical Data Book' contains the following timing info about (non-text mode) display lines.

Description Cycles Length

Synchronize signal [0 - 100) 100

Left erase time [100 - 202) 102

Left border [202 - 258) 56

Display cycle [258 - 1282) 1024

Right border [1282 - 1341) 59

Right erase time [1341 - 1368) 27

Total [0 - 1368) 1368



So one display line is divided in 6 periods. The total length of one line is 1368 cycles. The previous section showed how long individual VRAM accesses take. The next sections will figure out how all the required accesses fit in this per-line budget of 1368 cycles.



.......



TODO horizontal set-adjust: The numbers in the above table are valid for horizontal set-adjust=0. Similarly all our measurements were done with set-adjust=0. Using different set-adjust values will make the left/right border bigger/smaller. I still need to figure out which timing values of the next sections are changed by this. E.g. are all the VRAM accesses in a line shifted as a whole, or are just the bitmap data fetches shifted and remain (some) other accesses fixed?



TODO bits S1,S0 in VDP register R#9: The above table is valid for S1,S0=0,0. In other cases the length of a display line is only 1365 cycles instead of 1368. The rest of this text assumes a line length of 1368 cycles. I still need to figure out where exactly in the line this difference of 3 cycles is located.